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CWE-1303 — Vulnerability Class 1

1 vulnerabilities classified as CWE-1303. AI Chinese analysis included.

CWE-1303 represents a hardware-level weakness where shared microarchitectural resources, such as caches and branch predictors, fail to maintain strict isolation between distinct execution contexts. This vulnerability is typically exploited through side-channel attacks, where an adversary monitors timing variations or resource contention to infer sensitive data from a victim process. By analyzing these subtle performance fluctuations, attackers can reconstruct cryptographic keys or private information despite logical security boundaries. To mitigate this risk, developers must implement robust isolation mechanisms, such as cache partitioning and flush-on-context-switch protocols, ensuring that one process cannot observe the microarchitectural state of another. Additionally, utilizing hardware-enforced security features and minimizing shared resource dependencies are critical strategies for preserving confidentiality and preventing unauthorized information leakage in modern computing environments.

MITRE CWE Description
Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts. Modern processors use techniques such as out-of-order execution, speculation, prefetching, data forwarding, and caching to increase performance. Details about the implementation of these techniques are hidden from the programmer's view. This is problematic when the hardware implementation of these techniques results in resources being shared across supposedly isolated contexts. Contention for shared resources between different contexts opens covert channels that allow malicious programs executing in one context to recover information from another context. Some examples of shared micro-architectural resources that have been used to leak information between contexts are caches, branch prediction logic, and load or store buffers. Speculative and out-of-order execution provides an attacker with increased control over which data is leaked through the covert channel. If the extent of resource sharing between contexts in the design microarchitecture is undocumented, it is extremely difficult to ensure system assets are protected against disclosure.
Common Consequences (1)
ConfidentialityRead Application Data, Read Memory
Microarchitectural side-channels have been used to leak specific information such as cryptographic keys, and Address Space Layout Randomization (ALSR) offsets as well as arbitrary memory.
Mitigations (2)
Architecture and DesignMicroarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
RequirementsMicroarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
Examples (1)
On some processors the hardware indirect branch predictor is shared between execution contexts, for example, between sibling SMT threads. When SMT thread A executes an indirect branch to a target address X, this target may be temporarily stored by the indirect branch predictor. A subsequent indirect branch mis-prediction for SMT thread B could speculatively execute instructions at X (or at a locat…
CVE IDTitleCVSSSeverityPublished
CVE-2023-1998 Spectre v2 SMT mitigations problem in Linux kernel — Linux Kernel 5.6 Medium2023-04-21

Vulnerabilities classified as CWE-1303 represent 1 CVEs. The CWE taxonomy describes the weakness; review individual CVEs for product-specific impact.