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CWE-1257 — Vulnerability Class 2

2 vulnerabilities classified as CWE-1257. AI Chinese analysis included.

CWE-1257 represents a critical hardware design weakness where aliased or mirrored memory regions exhibit inconsistent access control enforcement. This vulnerability arises when hardware logic fails to synchronize permission checks across different memory mappings, allowing an untrusted agent to bypass security restrictions. Typically, an attacker exploits this by accessing a restricted memory region through its alias, effectively circumventing intended isolation mechanisms to read or write sensitive data. To mitigate this risk, developers must ensure that all memory aliases share identical, strictly enforced permission bits within the hardware’s memory management unit. Rigorous verification processes, including formal verification and comprehensive testing of memory mapping configurations, are essential to guarantee that access controls remain consistent across all mirrored regions, thereby preventing unauthorized privilege escalation or data leakage.

MITRE CWE Description
Aliased or mirrored memory regions in hardware designs may have inconsistent read/write permissions enforced by the hardware. A possible result is that an untrusted agent is blocked from accessing a memory region but is not blocked from accessing the corresponding aliased memory region. Hardware product designs often need to implement memory protection features that enable privileged software to define isolated memory regions and access control (read/write) policies. Isolated memory regions can be defined on different memory spaces in a design (e.g. system physical address, virtual address, memory mapped IO). Each memory cell should be mapped and assigned a system address that the core software can use to read/write to that memory. It is possible to map the same memory cell to multiple system addresses such that read/write to any of the aliased system addresses would be decoded to the same memory cell. This is commonly done in hardware designs for redundancy and simplifying address decoding logic. If one of the memory regions is corrupted or faulty, then that hardware can switch to using the data in the mirrored memory region. Memory aliases can also be created in the system address map if the address decoder unit ignores higher order address bits when mapping a smaller address region into the full system address. A common security weakness that can exist in such memory mapping is that aliased memory regions could have different read/write access protections enforced by the …
Common Consequences (3)
ConfidentialityRead Memory
IntegrityModify Memory
AvailabilityDoS: Instability
Mitigations (2)
Architecture and Design, ImplementationThe checks should be applied for consistency access rights between primary memory regions and any mirrored or aliased memory regions. If different memory protection units (MPU) are protecting the aliased regions, their protected range definitions and policies should be synchronized.
Architecture and Design, ImplementationThe controls that allow enabling memory aliases or changing the size of mapped memory regions should only be programmable by trusted software components.
Examples (1)
In a System-on-a-Chip (SoC) design the system fabric uses 16 bit addresses. An IP unit (Unit_A) has 4 kilobyte of internal memory which is mapped into a 16 kilobyte address range in the system fabric address map. System Address Mapped to 0x0000 - 0x3FFF Unit_A registers : 0x0000 - 0x0FFF 0x4000 - 0xFFFF Other IPs & Memory To protect the register controls in Unit_A unprivileged software is blocked…
In this design  the aliased memory address ranges are these: 0x0000 - 0x0FFF 0x1000 - 0x1FFF 0x2000 - 0x2FFF 0x3000 - 0x3FFF The same register can be accessed using four different addresses: 0x0000, 0x1000, 0x2000, 0x3000. The system address filter only blocks access to range 0x0000 - 0x0FFF and does not block access to the aliased addresses in 0x1000 - 0x3FFF range. Thus, untrusted software can leverage the aliased memory addresses to bypass the memory protection.
Bad · Other
In this design the aliased memory addresses (0x1000 - 0x3FFF) could be blocked from all system software access since they are not used by software. Alternately, the MPU logic can be changed to apply the memory protection policies to the full address range mapped to Unit_A (0x0000 - 0x3FFF).
Good · Other
CVE IDTitleCVSSSeverityPublished
CVE-2025-27032 Improper Access Control Applied to Mirrored or Aliased Memory Regions in Hypervisor — Snapdragon 7.8 High2025-09-24
CVE-2025-36600 Dell Client Platform BIOS 安全漏洞 — Client Platform BIOS 8.2 High2025-07-08

Vulnerabilities classified as CWE-1257 represent 2 CVEs. The CWE taxonomy describes the weakness; review individual CVEs for product-specific impact.