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CWE-1234 类漏洞列表 4

CWE-1234 类弱点 4 条 CVE 漏洞汇总，含 AI 中文分析。

CWE-1234 属于硬件配置保护绕过漏洞。攻击者通常在设备进入调试模式时，利用该状态下的特权绕过由固件设置的锁定机制，从而修改受保护的寄存器或地址区域，破坏系统完整性。开发者应避免在调试模式下暴露配置接口，或在进入调试状态前强制解锁并重新验证安全策略，确保关键配置在运行时不可被非法篡改。

MITRE CWE 官方描述
CWE：CWE-1234 硬件内部或调试模式允许覆盖锁定 英文：在调试模式下，系统配置保护可能被绕过。 设备配置控制通常由受信任的固件或软件模块（例如 BIOS/bootloader）在设备电源复位后进行编程，然后锁定以防止任何进一步的修改。这通常通过使用受信任的锁定位（trusted lock bit）来实现，当该位被设置时，会禁用对一组受保护寄存器或地址区域的写入操作。锁定保护的目的是防止对某些系统配置（例如内存/内存保护单元配置）进行修改。如果硬件设计中支持硬件或内部模式/系统状态所支持的调试功能，则可能允许修改锁定保护，从而允许访问和修改配置信息。
常见影响 (1)
Access ControlBypass Protection Mechanism
Bypass of lock bit allows access and modification of system configuration even when the lock bit is set.
缓解措施 (1)
Architecture and Design, Implementation, TestingSecurity Lock bit protections should be reviewed for any bypass/override modes supported. Any supported override modes either should be removed or protected using authenticated debug modes. Security lock programming flow and lock properties should be tested in pre-silicon and post-silicon testing.
Effectiveness: High
代码示例 (2)
For example, consider the example Locked_override_register example. This register module supports a lock mode that blocks any writes after lock is set to 1. However, it also allows override of the lock protection when scan_mode or debug_unlocked modes are active.
module Locked_register_example ( input [15:0] Data_in, input Clk, input resetn, input write, input Lock, input scan_mode, input debug_unlocked, output reg [15:0] Data_out ); reg lock_status; always @(posedge Clk or negedge resetn) if (~resetn) // Register is reset resetn begin lock_status <= 1'b0; end else if (Lock) begin lock_status <= 1'b1; end else if (~Lock) begin lock_status <= lock_status end always @(posedge Clk or negedge resetn) if (~resetn) // Register is reset resetn begin Data_out <= 16'h0000; end else if (write & (~lock_status | scan_mode | debug_unlocked) ) // Register protected
Bad · Verilog
Either remove the debug and scan mode overrides or protect enabling of these modes so that only trusted and authorized users may enable these modes.
Good · Other
The following example code [REF-1375] is taken from the register lock security peripheral of the HACK@DAC'21 buggy OpenPiton SoC. It demonstrates how to lock read or write access to security-critical hardware registers (e.g., crypto keys, system integrity code, etc.). The configuration to lock all the sensitive registers in the SoC is managed through the reglk_mem registers. These reglk_mem regist…
... always @(posedge clk_i) begin if(~(rst_ni && ~jtag_unlock && ~rst_9)) begin for (j=0; j < 6; j=j+1) begin reglk_mem[j] <= 'h0; end end ...
Bad · Verilog
... always @(posedge clk_i) begin if(~(rst_ni && ~rst_9)) begin for (j=0; j < 6; j=j+1) begin reglk_mem[j] <= 'h0; end end ...
Good · Verilog
CVE ID标题CVSS风险等级Published
CVE-2025-33242 NVIDIA B300 MCU 安全漏洞 — HGX and DGX B300 5.9 Medium2026-03-24
CVE-2025-59104 Dormakaba Access Manager 安全漏洞 — Access Manager 92xx-k7 6.8AIMediumAI2026-01-26
CVE-2023-44298 Dell PowerEdge Server BIOS 安全漏洞 — PowerEdge BIOS 3.6 Low2023-12-05
CVE-2023-44297 Dell PowerEdge Server BIOS 安全漏洞 — PowerEdge BIOS 7.1 High2023-12-05

CWE-1234 是常见的弱点类别，本平台收录该类弱点关联的 4 条 CVE 漏洞。